
Ph.D Candidate, 2010 expected
China

Ph.D Candidate, 2010 expected
China
• Strong programming skills:
C/C51/C++, Matlab, Verilog-A.
• Rich experience with lab instruments/equipments:
VNA/PNA, Spectrum Analyzer, Oscillographs, DCA, RF/DC Sources, Power Meter, IC-CAP, Load-pull System (Maury and Focus), Microwave Probe Station (Cascade and Suss) and so on.
• Skilled in circuit design/simulation software:
ADS, HSpice, Cadence, HFSS, Protel, AutoCAD, ThermoFlow, SystemVue.
• Very familiar with compound semiconductor technology and fabrication process. Plenty of hand-on experience with compound semiconductor (InP, GaAs HBT and GaN HEMT) clear room techniques.
• Strong mathematic and physics knowledge background:
Linear Algebra, Numerical Differential Equations, Random Process, Quantum Physics, Semiconductor Physics.
• Strong signal and system knowledge background:
Information Theory and Code, Communication Theory, Signal and System, Signal Integrity.
• Computer skill and foreign language:
Windows, Linux, UNIX, Solaris, fluent oral and written English.
(Semiconductors industry)
September 2005 — Present (4 years 4 months)
Research Area:
• High linearity and high power radio frequency power amplifiers design and fabrication in GaAs, InP HBT and GaN HEMT technologies.
• Ultra-high-speed analog and mixed signal integrated circuits design and fabrication (ADC, DAC, DDS) in compound semiconductor technologies such as GaAs, InP HBT.
• RFIC and MMIC (PA, LNA, Mixer and so on) design and fabrication.
• InP HBT based mm-wave devices and integrated circuits design.
• Compound semiconductor process research and development, device modeling.
(Semiconductors industry)
September 2008 — August 2009 (1 year )
This is a 2-order Gm-C continuous time Σ-Δ modulator used for ultra-high speed ADC. It includes two cascaded Gm-C cells, followed by a Cherry-Hooper amplifier, a 1-bit quantizer and a 1-bit RTZ DAC making the loop closed. The first Gm cell utilizes Caprio cell to increase its linearity and negative resistance network to increase its DC gain meanwhile maintaining a relative low voltage supply level. The quantizer and RTZ DAC are optimized to prevent metastability and dynamic hysteresis. Test results show 9.6-ENOB with 8GHz clock frequency and a 62.5MHz sine input analog signal. This Σ-Δ modulator occupies 1.8mm×0.8mm die area with about 200 HBT devices and consumes about 0.9W DC Power.
(Semiconductors industry)
September 2008 — August 2009 (1 year )
To demonstrate the performance of Win Semiconductor’s InGaP/GaAs HBT process for digital applications, we design this ultra-high speed frequency divider. Based on the master-slave flip-flops architecture, we make use of peaking inductors to get a higher operating frequency. The circuit layout is strictly symmetry to get a perfect matching, and all the high speed paths are EM-simulation verified. Test results give up to 20GHz operating frequency. This divider occupies 1.0mm×0.8mm die area with 34 HBT devices and consumes about 0.3W DC Power.
(Semiconductors industry)
September 2007 — August 2009 (2 years )
This work is an Ultra-high-speed Direct Digital frequency-Synthesizer based on Win Semiconductor’s 1um InGaP/GaAs HBT process. As the leader of a 3-student research group, in charge of the system-level design, transistor level schematic design and the layout work. This ultra-high-speed DDS eliminates the using of ROM which is an essential part in traditional DDS structure, making up a ROM-less architecture which includes a 4×2-bit pipeline accumulator, a binary-to-thermal coder, a sine-weighted nonlinear DAC and a Gilbert multiplier. To pursuit as high speed as possible, all the digital circuit blocks take Dual-Edge-Trigger ECL architecture. On-wafer test results show that this DDS can work correctly with up to more than 10GHz clock, output high-purity sinusoidal wave between DC to 5GHz under the control of 8-bit input frequency control word giving a worst SFDR of 26dBc. This DDS occupies 2.4mm×2.0mm die area with about 2000 HBT devices and consumes about 2.5W DC power.
(Semiconductors industry)
September 2007 — August 2009 (2 years )
In order to get a much better output sinusoidal wave performance, we create this innovative DDS architecture based on the previous design. Instead of aborting the 3-LSB of the 8-bit accumulator’s output results as the previous design does, we make use of this 3-LSB to addressing a 8×8×3-bit ROM for output waveshape correction. To trade off the increased circuit complexity coming with ROM addressing and readout circuits, all the digital circuit blocks take single-edge-trigger ECL architecture. So the maximum operating clock is 6GHz, much lower than the previous design. However, because of the addition of waveshape correction ROM, this DDS can give more than 18dBc improvement of SFDR. On-wafer test results show that this DDS can work correctly with up to more than 5GHz clock, output high-purity sinusoidal wave between DC to 2.5GHz under the control of 8-bit input frequency control word giving a worst SFDR of 45dBc. This DDS occupies 2.4mm×2.0mm die area with about 2000 HBT devices and consumes about 4W DC power.
(Semiconductors industry)
July 2008 — September 2008 (3 months)
Based on our 4-inch InP DHBT process, design a 94GHz power amplifier MMIC. The device’s large signal model is established by on-wafer testing and parameters extracting using IC-CAP and microwave probe station. With common-emitter plus common-base Cascode topology and operated as Class A, this PA MMIC adopts conjugated input and output matching networks for optimum power gain and linearity. The design optimizations for the thermal-stability and electric-stability are also included in the design procedure. With CPW on InP substrate as transmission lines, the fabricated PA MMIC gives 6.1dB linear power gain with 3dB bandwidth of DC~103GHz, 16dBm saturation output power, less than -20dB input/output matching and more than 30dB isolation.
(Semiconductors industry)
August 2007 — April 2008 (9 months)
Based on our 4-inch InGaP/GaAs power HBT process, design a 5.9-6.4GHz 4W continuous-wave power amplifier MMIC. The tasks include, but not limited to, material system design, device modeling, circuit design and electromagnetism simulation verification, MMIC fabrication, circuit test. All the simulations have been finished now, but because of our clear room is unavailable for GaAs HBT process now, this work is delayed.
(Semiconductors industry)
November 2006 — June 2007 (8 months)
A 13.75-14.5GHz 50W power amplifier module is designed for the VAST application. The specification requires 50W pulsed (max duty cycle 20%) output power with no more than 10dBm input power and PAE should be better than 20%. The tasks include microwave amplification link circuits design, DC bias circuits design, modulations and control circuits design, framework and mechanism design, and so on. The involved software and equipments include, but not limited to, DXP 2004, ADS, HFSS, AutoCAD, vector network analyzer, spectrum analyzer, power meter, DC/RF signal source. This module has been employed in many commercial products.
(Semiconductors industry)
July 2006 — December 2006 (6 months)
As leader of a 3-student research group, be responsible for the GaN HEMT dies based hybrid-integrated traveling wave amplifier design. Complete the simulation and micro strip PCB design using ADS, bond-wire encapsulation and test. Performance: 2-18GHz, 10dB Gain, 0.1dB flatness. Future work is developing full-integrated high performance traveling wave amplifiers based on GaN HEMT process technology.
(Semiconductors industry)
September 2006 — November 2006 (3 months)
This project was one of the pre-research works of GaAs/InP HBT ultra-high-speed DDS (Direct Digital frequency Synthesizer) chip. The purpose was to reveal how the DDS work and give directions for future work. Developed a DDS test circuit board so that one can write frequency control word in-systemly through PC MCU AT89S52 DDS chip AD9850 and then get the sine output signal up to 72MHz real-timely. The tasks included circuit design (DXP 2004), MCU programming (Keil C51) and PC programming (Visual Studio .Net).
(Design industry)
April 2004 — July 2004 (4 months)
Developed the whole system of Industrial-Control-Computer based vision identifying system for the Asia 2004 RoboCon. Be responsible for MCU and computer programming and periphery circuits design. The system can receive vision information of targets through CCD camera, process these information (about 28ms/frame) so that it can control the Robot’s movement real-timely.
(Design industry)
August 2003 — October 2003 (3 months)
As a team leader, be responsible for the hardware and software co-design including MCU circuits design, motor-driving circuits design, MCU programming and mechanism design for our robot named Six-Feet Creeper. Worked with the other 3 teammates together, we got the “Best Technique Team Award” of USTC 2003 RoboGame.
Ph. D , Micro Electronics , 2005 — 2010 (expected)
B.S. , Electronic Engineering , 2001 — 2005
RF/MW PA Design, Analog and Mixed Signal IC Design, Basketball, Swimming, Reading...
• Zhang Zongzhi Scholarship, 2003 USTC.
• Best Technique Team Award, 2004 USTC-RoboGame.
• Outstanding Grad Award, 2005 USTC.
• Excellent Graduate Student Award, 2006 IMECAS.
• Excellent Graduate Student Award, 2007 IMECAS.
• Excellent Graduate Student Award, 2008 IMECAS.
• Best Customer Paper Award, 2008 Agilent EESof.
• IMECAS Director Special Award, 2009 IMECAS.
• Best Customer Paper Award, 2009 Agilent EESof.